Before using the ACPMU it is important to understand a few things. 

1. The ACPMU works by using one delay generator as a reference point and varying another delay generator to find the optimum measured interval.  In our example to follow, one timing generator creates an event in time as a stimulus edge that is going to an input to the chip, while another timing generator creates a different event in time as it is used to compare the DUT output signal.
2. Proper use of the stimulus formats is crucial to ACPMU effectiveness.  NRZ format is generally fine for many pins, but other pins such as clock and enables may need to be dynamic; that is, RZ or R1, so that trailing edges can be controlled for tests like Pulse Width.
3. The vectors play a key role in the operation:
1. Measurements are made based on the pass/fail point of output pins, so you must have functional vectors that pass in order to use ACPMU.
2. The entire vector set is executed and so your control of which transition is used for measurements is limited.  You may need some special small vector sets for better control of the measurements.
3. If you make the mistake of using NRZ for your clock with the clock pin toggling at every other vector (i.e., vector data is 1,0,1,0) then you will have to run your test rate at twice the desired test rate, hampering use of the ACPMU. Since ACPMU can only measure within one clock cycle, you will not be able to do most tests because your data requires two cycles in order to change.
4. ACPMU uses binary search to find the measurements, not a linear search.  This makes it much faster while providing 100ps granularity in the final measurement.
5. The ACPMU searches for the transition point in the vector run where the output result goes from PASS to FAIL, or from FAIL to PASS.  To successfully take the measurement, this Pass/Fail transition point must be within the defined Measurement Range.  Defining the proper range enables the ACPMU to search for the first moment when the output data becomes valid (i.e., access time), or the last moment when output data becomes invalid (i.e., hold time).

The test type is “Access Time”, but we’ll call our test “PROP DLY”; for our purposes it essentially means the same thing.  When we click the “Ref. Pin…” button we select the clock pin, and the reference delay generator (6) is automatically selected.  The currently assigned value for the leading edge is displayed.

For our variable, we have selected the output pins Q0-Q3 as displayed in the Pin List.  Symphony automatically selects an unused delay generator so that no other pins are affected, but you can click “Manual select” and choose another delay if desired.

Next we set our measurement range.  To determine the optimum range, we refer to the specifications for the 74F163, which states that the maximum allowed propagation delay is 10.0ns.  We know that our device passes functional vectors with the output compare delay generator set at 30ns.  Since our clock leading edge occurs at 12.0ns, this means that we are allowing 18ns for prop delay during functional test.  So our actual prop delay is somewhere between 0ns and 18ns (18ns is actually too “generous” for this chip).  The device is considered “bad” if the measured value is more than 10ns, so we will set our range at 0 to 12ns.  The start and end times of the range are not relative to the “time zero” of the test rate, but are relative to the leading edge of the clock pin.

Again, it is important that our Measurement Range is set so that the output of the device will pass at one end of the range and fail at the other end.  In our case, 0ns will cause vectors to fail because it is too near to the clock transition.  Surely it will be passing before it reaches 12ns.  Negative values are allowed in the range setting as long as the range still fits within a single vector timeframe.

When we start the test Symphony will repeatedly run the functional vectors while adjusting the compare strobe delay generator across the measurement range in a binary search algorithm.  The results appear in the file ACPMU.LOG.

Other tests in ACPMU

In the case of a Setup Time measurement, we measure for the minimum amount of time required for input data to be asserted before it is clocked in by the leading edge of the clock pin.  The reference pin is the clock pin, and the variable is the leading edge of the data (data inputs should be defined as RZ for this test so that the trailing edge of the data does not move as a function of “Variable”).  For the type of variable you can select “Input Transition”. The range will be from the start of the Test Rate cycle (time zero) up to the leading edge of the clock pin.  When the data is asserted “too near” to the clock pin leading edge, the vectors fail because there is not enough setup time before the clock.  ACPMU will search the range between T₀ and CLK_LE to find the optimum setup time.