The delay generator shown as the "Inhibit" delay in the Pin Setup window displays the timing value for the Inhibit time. Essentially, this delay value indicates "when" the HiLevel driver goes tri-state during any given test clock cycle (vector) in which a "Z" appears as vector data. Below, see how vector data will look on five different tester channels, each employing one of the Stimulus Formats. Note that Rinh (Return to Inhibit) does not really have any considerations in this issue, because the Inhibit Delay is set to the same value as the leading edge delay automatically.

NRZ - Non-Return to Zero. Leading Edge delay (D_LE) set to zero nanoseconds.
DNRZ - Delayed NRZ. Same as NRZ but the Leading Edge delay is set to 20ns.
RZ - Return to Zero. "Dynamic". Leading Edge set to 20ns, Trailing Edge = 40ns.
R1 - Return to One. "Dynamic". Leading Edge = 20ns, Trailing Edge = 40ns.
Rinh - Return to Inhibit. "Dynamic". Leading Edge = 20ns, Trailing Edge = 40ns.

Test Rate: 15MHz, 66.666ns period.
Test Vectors, all pins: 0,1,Z,0,Z,1 (six vectors)

The slight appearance of some delay of the leading edge in these graphics is done only for clarity. The leading edge delay times are set to zero but the display places the edge slightly off of the gray cycle boundary line for easy viewing.

Example 1
In this example, we see that vector data continues to be asserted until the inhibit time occurs (which is set to the same delay value as the leading edge). This mode is not recommended unless you have some particular reason for stimulus data to be active during some portion of the cycles (vectors) in which a "Z" appears as the data.

Example 2
Here we see that setting Inhibit Delay to zero nanoseconds insures that the tester driver will be tri-stated for the entire vector when a "Z" appears as vector data. Most applications perform correctly when this practiced is used. Consequently, HiLevel recommends this approach for new users, applications, or as a starting point whenever you are unsure about the issue.

Other issues pertaining to Inhibit

When the functional test begins (by hitting the RUN button or the TestBox button) the HiLevel drivers will be tri-stated at the start of the first vector. They will not assert data until the leading edge time occurs, all on a per-pin basis. This occurs only after the DUT supply has powered up and settled out.

Tri-stated driver pins that are forcing data into a large fixturing mass such as long prober cables or some heavy capacitance may not appear to be at the tri-state level when viewed on an oscilloscope. This is due simply to the "charging" of this mass. The HiLevel drivers are indeed tri-stated, but without sufficient load on the DUT or fixture to "drain" the charge, it may appear to you and to your device that the line is still active. To see the driver go into Hi-Z without the effect described, remove your fixture and place a bare DUT board on the system. Restore the same SET and TRN file and then probe the suspect pin again. You should see normal tri-state behavior.

Also see:
Q'nApps #S17 Stimulus Formats
Q'nApps #S18 Prober Fixtures