#36 - MemTest Functional Description

#L36

Q: What is the functional description of HILEVEL's Memory Test feature?

Memory Test - Functional Description

Stimulus Data has special meaning when the ETS is in Memory Test mode. Each byte of stimulus data (for memory address/data only) controls special functions within the Memory Test circuitry of the Pin Electronics. The specific functions are determined by the selected Algorithm.

Stimulus Values Pertaining to Memory Test

When referencing the table below, refer also to the Memory Test Functional Diagram. The following information applies to each byte of stimulus data for both address and data.

Note that stimulus bit 7 functions as a strobe to the memory test circuit and is indicated as Memory Edge in the Pin Setup Window. Edge refers to the 'active' edge of the strobe.

Stimulus	Function	Comments
0x00- 0x01 0x90 0xA0 0xA1 0xB1 0xC0- 0xCF	NOOP y = CONSTANT y = f(x) y = f(x2) y = f(x/2) __ y = f(x) _____ y = f(x) +1 Load CONSTANT*	No operation. Most commonly used to load/reload initial value used by the specified Algorithm. Output previous result (effectively a NOOP). Shift left one bit position, insert '0'. Shift right one bit position, insert '0'. Complement. LS 4 bits are loaded into LS byte of 32-bit CONSTANT (bits 0-27 of CONSTANT are left-justified).

NOTE: The specific FUNCTION (increment, shift) is determinrsd by the selected Algorithm. The input vectors have direct control over carry/serial input, complement, loading of CONSTANT register only.

Bit 7 of each stimulus byte is an RZ stimulus bit. This stimulus bit clocks the FUNCTION results into the OUTPUT register of the memory test circuit and loads/shifts data into CONSTANT, four bits at a time. The trailing (clocking) edge of this stimulus bit is defined by Memory Edge in Pin Setup.

Under normal operation, vector data is applied to the DUT exactly as defined in Pin Setup. However, when Memory Test is selected, vector data controls special functions used in the generation of specific patterns which are determined by selected algorithms. Therefore, the expected response data reflects the response expected as a result of the applied stimulus from the Memory Test circuit and not the Vector Stimulus. For example, if a Checkerboard pattern is chosen under Algorithms in Memory Test Setup, the expected response will be either 0x55 or 0xAA, while the vector stimulus will appear as previously defined under Stimulus Values Pertaining to Memory Test. In order to ease confusion and facilitate debug/verification, a special 'Pin Direction' is automatically selected in Pin Setup. 'Split Memadr' and 'Split Memdata' allow the user to view (in Analysis) Stimulus Data both as it is input to the Pin Electronics (to Memory Test), and as it is input to the DUT (from Memory Test) within the same test cycle.

The diagram below applies both to memory address and memory data. It is repeated for each byte of address or data. Also, see Example 1.

block diagram

Memory Test Functional Diagram

Mem vectors
Memory Test Vectors

00005-
0000C

0000D

0000E-
00010

00011

00012

00013-
00014

00015

00016

Loads '00000000' into 32-bit CONSTANT for each byte of address stimulus.
Loads '55555555' into 32-bit CONSTANT for data stimulus.

Loads OUTPUT Registers with CONSTANTS for address and data stimuli.
(i.e. address='0000', data='55' - See NOTE)

Performs no operation relative to memory stimulus. These vectors set up
the loop count in preparation for generating memory write stimulus.

This vector increments the address and complements the data stimulus for
each test cycle (determined by Memory Edge timing). The test loops on this
vector (decrementing the loop count each cycle), until the count reaches zero.

Loads OUTPUT Registers with CONSTANTS (i.e. address='0000', data='55')

No operation for memory stimulus. Sets up loop count in preparation for
generating memory read stimulus. Note that the loop count reflects the fact
that there are 2 memory read cycles for each decrement of the count.

Compares memory data (from DUT) with expected data '55' and increments the
address stimulus. The loop count is decremented.

Compares memory data (from DUT) with expected data 'AA' and increments
the address stimulus. If the loop count has not decremented to zero, vector
00015 is repeated.

Description of Vectors

NOTE: Although only 15 bits of address and 8 bits of data are significant, all functions are performed with 32-bit operands.

Also See:

Q'nApp #L1: PinList
Q'nApp #L4: Using Memory Test

QL36.zip is a zipped Word file of this Q'nApp.

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