#E4#E4
Q:
How can I test memories with ETS2k?
Testing a 256K x 4 DRAM Under ETS2k
| The Memory Test feature of the ETS is
possible because
of the tremendous versatility of the HiLevel proprietarty gate arrays
that
control the ETS pin electronics. The powerful ETS2k software redefines
the functions of these chips so that very deep memory devices can be
tested
using very few vectors. When using the ETS for Memory Test the software
takes control of the vectors and the pattern generator program, so it
is
important that you not modify these resources manually.
It is very important to plan ahead for Memory Test, particularly when building up your DUT board. This is due to the way in which the pin electronics boards are assigned for specific purposes. PE board #1 (pins 1-32) is used for the memory address pins of your device. ETS2k will control these pins like a counter, sequencing through memory addresses as part of a pattern generator loop. PE board #2 (pins 33-64) will function as the data I/O pins to the memory device under test. PE board #3 (pins 65-96) provide control pin functions for your memory device, such as output enables, chip enables and read/write pins. You can use the PinList import feature to assign your pins and names, or do it manually from the Main Test setup window. Just be sure to assign pins according to their types as illustrated in the above paragraph, and in accordance with your DUT board wiring. Here are the main steps in preparation. You can also use the ETS2k User Manual for more assistance. |
Begin the setup by checking the Memory Test box on the "Modes" area of the Main Setup window:
| There are
three suggested Control Pin configurations. Don't worry if none match
your configuration exactly;
you can edit the PinList file to match your
needs. |
 |
| The ETS2k software supports these standard algorithms. Just use the scroll buttons to select one for your first test. Later, you can select different ones to create more vector sets. |  |
| The PinList shown below is the result of clicking the PinList button after your configuration has been defined. Save this file after you have typed in your DUT pin numbers and made any other changes. Then press the Set file button to import the PinList. | |
Example
from a PinList file for Memory Test
| The pin TYPEs
SMA and SMD in the PinList file
mean "Split Memory Address" and "Split Memory Data", as can
be seen as the Pin Direction in the Pin Setup area of the Main Setup
window. Do
not change these settings. |
 |
| You will also
notice that for the Address and
Data groups (groups 1 and 2) that the timing section of the Main Setup
window
has changed. The "Trailing
Edge" field is now called "Memory Edge". |
 |
| Now you can
define your DUT power supplies,
logic levels, and test rate. You will
see that the sequencing mode is set to Memory Test. Do not change this
setting. Save
your Set file for future loading. |
 |
| Select a Test Pattern from the Algorithm box in the MemoryTest Setup section. For your first pattern, it is common practice to use CheckerBoard. | |
If you open the Vectors window, you can see your assigned pin groups displayed. You'll also see random, unmeaningful data as the vectors (see below). Press the HATGOL button on the Memory Test section of the Main Setup window. This action will cause the Comment field of the Vectors window to be filled with the HATGOL statements necessary to translate vectors for the selected test pattern, as can be seen in example on the next page. Refer to the HATGOL manual for details about these instructions and commands in the Comment field. |
|
Vector Window
Before HATGOL Button is Pressed
| In the vectors Comment field, some definitions may need to be modified prior to translating, i.e. 'WRITE', 'READ', and 'default'. Each of these is preceded with the '#define' statement. Initially these will be all ones. The order of bits for these binary values is determined by the 'consign' statement, which is used to assign the appropriate control pins to the 'Control' group referenced by the HATGOL 'control' statement. For example, if groups /WRITE, /OE, and /CS (all active low) are groups 3, 4, and 5 respectively, and are 'consigned' as 3 4 5, then modify the 'WRITE' definition from 0b_111 to 0b_010 and modify the 'READ' definition fomr 0b_111 to 0b_100 ('0b_' denotes binary). Reference the HATGOL Manual for more detailed information. |
| After making any modifications, merely press the 'Translate' button labeled [HT] on the main toolbar (top of window). This action will cause the HATGOL to be translated into vectors, as seen on the next page. The HATGOL program can be edited at any time for changes, but you must hit the "HT" button again to translate your changes into vectors. |
| Memory Test
vectors are actually more like
instructions for the HiLevel pin electronics, so at first they do not
look like
what you may expect. When you click
your RUN button, the actual (and more meaningful) vectors can be seen
in the
Analysis window, where you’ll see actual memory addresses and
data. By using this Algorithmic Instruction
method, very large memories can be tested with just a few hundred
vectors. After creating these vectors, be
sure to
upload the TRN and PRG files along with the Set file. |
Also See:
Qe4.zip is a zipped Word file of this Q'nApp.
Click your browser's Back button to return to the
Q'nApps
index.