For some tester manufacturers, the question of the "true" definition of data rates (or clock rates) has been an issue of "specmanship" more often than it has been of service to those seeking the "truth". Since these variations can be frustrating, we at HiLevel would like offer our definition of data and clock rates and try to help you understand how other views can vary.

What Happens in the ETS?
One of the most important points we wish to make clear is that the HiLevel basic program cycle is 20ns (i.e., 50MHz). This means that data is retrieved from RAM, formatted, processed and driven (as well as received in the case of DUT outputs) all within a single program cycle, including loops, branches and other programmed instructions. Not all testers do this; some employ muxing tricks, with the resulting idiosyncracies. We put a great deal of effort into developing a custom chip specifically for the purpose of performing these operations in a single cycle.

Obviously a higher clock rate compels the need for better resolution. Pin-to-pin skew is equally important for insuring accuracy at higher speeds. At 500MHz, how meaningful is a 2ns cycle time if the edge placement resolutions is no better than 100ps? The HiLevel ETS770 delay resolution is 50ps, allowing for excellent resolution in such situations. And where skew relationships are extremely critical, we provide the tools for manual deskew between pins in critical data paths.

Bidirectional Data
HiLevel's classification of the basic data rate is somewhat simplistic; the "Test Rate" as defined in the Run Setup window reflects the bidirectional data rate. You can provide stimulus to the device at 2X, 3X or 4X the data rate (or "Test Rate" defined in the Run Setup window), but the acquisition of DUT output data is done at 1X -- in other words, at the defined Test Rate.

Stimulus Data
To acheive 2X, 3X or 4X stimulus data rate, the Timing On-the-Fly feature is employed (TOF). This feature is covered in the ETS manual and the online Help file that comes with your ETS2k software. Some additional system resources are consumed in this mode, but data rates of up to 200MHz are possible with TOF. See the example of how a 200MHz clock is created.

Other Views
Some users and tester manufactures define an edge transition as being the delimiter in determining actual test rate. In other words, if RZ or R1 data format is selected then two edge transitions are encountered during each test cycle and the perceived test rate is double that of the defined test rate. If this philosophy is employed, the ETS780 (a 50MHz test system) is capable of delivering a 400MHz stimulus test rate, referring to the example below. However, HILEVEL prefers to retain the undisputable premise that the actual "Test Rate" is as defined in the Run Setup window. You may draw your own conclusions regarding views other than the conventional.

What Next?
Will HILEVEL produce a system with test rates beyond 50MHz? Most certainly, we already have. We've already introduced the Griffin and the Titan, capable of speeds of up to 200MHz. Presently, our gate arrays can perform all system functions in real time -- everything is done on the fly in 20ns with no tricky muxing. It's just a matter of making this (currently) six-micron architecture even faster. Of course, we will always offer an attractive upgrade path for HiLevel customers. And as always, your setup and vector files will be easily transportable from older to newer systems.

Keep watching for the release of new HiLevel products; sign up on our email list to receive notices automatically! Just go to the signup page at http://hilevel.com/emailist.html. You can learn more about HiLevel products on our homepage, including new application notes and announcements of upcoming events.

Qe24.zip is a zipped Word file of this Q'nApp.

Also see:
User Manual Section 20: Timing On-the-Fly